The 3D3D16G32WB2650 is a high speed stack multi-chip package integrated 8Gbits x2 DDR3 SDRAM and fabricated with ultra-high performance CMOS process containing 16Gbits which is organized as 64Mbits x 8 banks by 32 bits.
This synchronous device achieves high-speed double-data-rate transfer rates of up to 1333 Mb/sec/pin (DDR3-1333) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) On-die termination, (4) programmable driver strength data, (5) seamless BL4 access.
All the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional differential data strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a RAS# and CAS# multiplexing style.
The 16Gb DDR3 device operates with a single power supply: 1.5V (or 1.35V) for VDD and VDDQ.
This device is ideal for high density memory applications that require high-speed transfer and compatibility with standard servers and networking equipment.
