The Memory Controller is defined by the previously described UIF and the DIF, compliant to DFI 2.1, to send commands and data to the DDR memory components through the DDR PHY (which is uniquely configured to work with specific FPGAs/ASICs).
SPACE TECH EXPO EUROPE 2026
Discuss your project in person with our sales team, from component selection to design-in. We will set aside 30 minutes for you.
SPACE TECH EXPO EUROPE
Besprechen Sie Ihr Projekt persönlich mit unserem Vertriebsteam, von Bauteilauswahl bis Design-in. Wir nehmen uns 30 Minuten Zeit.