The Radiation Intelligent Memory Controller (RIMC DDR3) is a fully configurable DDR3 SDRAM memory controller IP core designed to work with 3D PLUS DDR3 memory modules to achieve radiation tolerance improvement. The RIMC contains all standard functions of a DDR memory controller for data width applications from 8b up to 144b. It includes alsoadditional functions, such as Single Event Upset (SEU) mitigation and Single Event Functional Interrupt (SEFI) protection (later described in paragraph 4.2) to be able to work in radiation environments.
In addition to the memory controller IP within the RIMC IP core, the user can either select PHY IPs provided in the IP core or develop its own PHY IP.
The RIMC has two primary interfaces, the user interface (UIF) and the DDR memory interface (DIF).
The UIF is comprised of at least one AHB bus, AXI bus or UPI, and also contains an APB bus for user dynamic configuration:
The Memory Controller is defined by the previously described UIF and the DIF, compliant to DFI 2.1, to send commands and data to the DDR memory components through the DDR PHY (which is uniquely configured to work with specific FPGAs/ASICs).
