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3D PLUS 80-Bit DDR4: Working Memory and Error Correction for Space Computing

How can high-capacity working memory be combined with resilient error handling in spacecraft computers? In our Space Tech Expo Europe 2025 interview, Wissam Mouallem, Sales Director at 3D PLUS, introduces a DDR4 SDRAM module with an 80-bit interface. Following our interviews on COMBO and MNEMOSYNE, this conversation explores a different layer of spacecraft memory architecture: volatile processing memory for processor- and FPGA-based systems.

Why 80 Bits? 64 Data Bits and 16 Bits for Error Correction

The focus is the 3D4D64G80LB2860 DDR4 module, organised as 1G × 80 bits and built from ten 8 Gbit DDR4 devices. For each memory word, 64 bits carry application data while 16 additional bits are reserved for error-correcting code (ECC) information. This yields 64 Gbit, or 8 GB, of usable data capacity, with another 16 Gbit physically available for ECC redundancy. The complete raw organisation therefore represents 80 Gbit.

3D PLUS provides the module in a BGA-363 package, specifying up to 2400 MT/s, a 1.2 V DDR4 supply and an operating-temperature option spanning −55 °C to +105 °C. The data-rate figure describes transfers per second, not a guaranteed application-level bandwidth. Other modules in the DDR4 space-memory family span 16 to 64 Gbit with x48, x72 and x80 interfaces.

ECC Is a System Capability, Not Just a Bus Width

The extra 16 bits provide space for stronger error-correction schemes. Actual fault detection and correction, however, depend on the memory organisation, controller, ECC algorithm and overall system configuration. An 80-bit interface does not, on its own, eliminate radiation-induced errors.

To support the wider memory subsystem, 3D PLUS offers its Radiation Intelligent Memory Controller (RIMC, 3DIPMC0815), a configurable DDR4 controller IP core. According to the manufacturer, it supports ECC and mitigation of Single Event Upsets (SEUs) and Single Event Functional Interrupts (SEFIs). A separate DDR4 Termination Regulator (3DPM0424) supplies the VTT termination network. Memory, error handling and electrical interfaces need to be engineered together.

The Microchip PIC64-HPSC Ecosystem

In the interview, Mouallem refers to a Microchip ecosystem for the next generation of space processing. This refers to PIC64-HPSC (High-Performance Spaceflight Computing), a 64-bit RISC-V microprocessor, not an FPGA. Microchip explicitly lists 3D PLUS in its PIC64-HPSC ecosystem as a supplier of 80-bit DDR4 memory supporting advanced error-correction capabilities.

This is a concrete system-level reference. The PIC64-HPSC memory interfaces support 72-bit configurations and an optional 80-bit mode. Depending on the implemented ECC scheme, the 80-bit interface enables multi-bit error correction and protection against an individual memory-chip failure. The actual level of resilience depends on the system configuration. More broadly, 3D PLUS DDR4 can also be used with suitable processors and FPGA designs, subject to controller, PHY and interface verification.

Radiation, Integration and Qualification Considerations

For its DDR4 family, 3D PLUS specifies total ionising dose (TID) above 100 krad(Si) and a single-event latch-up (SEL) threshold above 62.8 MeV·cm²/mg. These are manufacturer-published radiation figures associated with particular test conditions. They do not establish that a complete memory subsystem will be error-free in orbit. Designers still need to evaluate SEU and SEFI behaviour, ECC, memory scrubbing and recovery mechanisms at system level.

Procurement and design reviews should confirm the exact part number, applicable datasheet revision, temperature range and selected screening or qualification grade. 3D PLUS offers several quality options. Signal integrity, power integrity, pin assignment, thermal integration and DDR4 controller/PHY interoperability are further points to verify against the actual target architecture.

COMBO, MNEMOSYNE and DDR4: Three Different Memory Roles

The interviews with Wissam Mouallem cover three distinct tasks in a spacecraft computer. COMBO manages FPGA boot and configuration images. MNEMOSYNE stores non-volatile information such as configuration data or processor boot code without continuous power. DDR4 supplies high-speed volatile working memory during data processing. These functions may all be relevant to a spacecraft architecture, but that does not establish a specific combined product implementation.

We previously introduced the technical features of the 80-bit module in an MSA product article. The interview adds context around bus width, error correction and the wider space-computing ecosystem.

Meet 3D PLUS and Our Team at Space Tech Expo Europe 2026

3D PLUS will be joining us as a co-exhibitor at Space Tech Expo Europe in Bremen, 17–19 November 2026. Visit its team in Hall 5, Booth F11, for technical discussions about DDR4, memory architectures and radiation requirements.

Our extended team, with colleagues from MSA Components and Hi-Rel Solutions by Steliau Technology, will also be available there for your technical and project-related questions.

Arrange a technical discussion with our team in Bremen:

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