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4 Gbit DDR2 SDRAM (3D2D4G72UB3652)

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It is organized with 4 chips of 1Gbit + 1 chip for ECC. It is particularly well suited for use in high reliability, high performance and high density system applications, such as servers or workstations.
The 3D2D4G72UB3652 is packaged in a 191 balls BGA available with lead-free or leaded balls.

Fabio Asti

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Fabio Asti
Business Developement Manager
+39 342 198 3878 fabio.asti@steliau.it
  • Organized as 64M × 72.
  • Supply voltage: 1.8 V ± 0.1 V.
  • JEDEC standard 1.8 V I/O (SSTL_18 compatible).
  • Maximum data rate: 667 Mbps.
  • Differential data strobe per byte.
  • 4n-bit prefetch architecture.
  • DLL to align DQ and DQS transitions with CK.
  • 8 internal banks per die for concurrent operation.
  • Programmable CAS Latency.
  • Posted CAS Additive Latency.
  • Write Latency = Read Latency − 1 tCK.
  • Programmable Burst Lengths:

    • 4
    • 8
  • On-Die Termination (ODT).
  • 191 leaded or lead-free balls.
  • Available temperature ranges:

    • 0°C to +70°C
    • -40°C to +85°C
    • Specific temperature range available upon request.
  • Available with screening option for high reliability applications (Space, etc.).

Description

The 3D2D4G72UB3652 is a high-speed highly integrated DDR2 Synchronous Dynamic Ram Memory.

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