8 Tbit TLC/2.67 Tbit SLC NAND Flash (3DFN8T16LB2821)

• ONFI 4.2 compliant
• JEDEC NAND Flash Interoperability (JESD230D) compliant
• Triple-level cell (TLC) supporting p-SLC mode
• Page size x8: 18,352 bytes (16,384 + 1,968 bytes)
• Block size: 2,112 pages (33,792K + 4,059K bytes)
• Plane size: 4 planes × 556 blocks
• NV-DDR3 I/O performance
  • Up to NV-DDR3 timing mode 12
  • Clock rate: 1.67 ns (NV-DDR3)
  • Read/write throughput per pin: 1.6 GT/s
• SLC array performance
  • Read page operation time: 40 μs (TYP)
  • Program page time: 170 μs (TYP)
  • Erase block time: 8 ms (TYP)
• Dual operating voltage supply
  • VCC: 2.35 to 3.6 V
  • VCCQ: 1.14 to 1.26 V
• Data must be randomized by the external host before being input to the NAND device
• On-die termination (ODT) supported
• Endurance: 60,000 P/E cycles in p-SLC mode
• Operating temperature: -40 °C to +85 °C

Radiation Data in P-SLC Mode

• SEL LETTH: > 62.5 MeV·cm²/mg
• HCE LETTH: ≤ 32.4 MeV·cm²/mg
• SEFF LETTH: > 45.8 and ≤ 55 MeV·cm²/mg
• SEU LETTH: ≤ 1.5 MeV·cm²/mg
• SEFI LETTH: ≤ 1.5 MeV·cm²/mg
• Total Ionizing Dose (TID): > 25–30 krad(Si)*

*: TBC

Description

The use of the p-SLC mode combined with 3D PLUS stacking technology, provides a Flash memory with an area efficient solution for ultra-high-density storage and high-speed data transfer needs. It is packaged in a 215-ball BGA.

Downloads

• 3D Plus Memory Module P/N Decoder

Manufacturer Info

• www.3d-plus.com