The Radiation Intelligent Memory Controller (RIMC) is a fully configurable DDR2 SDRAM memory controller IP core designed to work with 3D PLUS DDR2 memory modules to achieve improved radiation tolerance. The RIMC contains all of the standard functions of a DDR memory controller for data width applications from 8b up to 64b, and additional functions, including Single Event Upset (SEU) mitigation and Single Event Functional Interrupt (SEFI) protection (later described in paragraph 4.2) to be able to work in radiation environments.
In addition to the memory controller IP within the RIMC IP core, the user can optionally select any of a number of 3D PLUS provided PHY IP or the user can develop their own PHY IP.
The RIMC has two primary interfaces, the user interface (UIF) and the DDR memory interface (DIF).
The UIF is comprised of at least one AHB bus, AXI bus or MIG, and also contains an APB bus for user dynamic configuration:
The Memory Controller is defined by the previously described UIF and the DIF, compliant to DFI 2.1, to send commands and data to the DDR memory components through the DDR PHY (which is uniquely configured to work with specific FPGAs/ASICs).
