RIM C – DDR4 SDRAM Controller IP Core (3DIPMC0744-2)

The Radiation Intelligent Memory Controller (RIMC DDR4) is a fully configurable DDR4 SDRAM memory controller IP core designed tocontrol 3D PLUS DDR4 memory modules and to achieve radiation tolerance improvement. The RIMC contains all standard functions of a DDR memory controller for data width applications from 8b up to 80b. It also includesError Correction Code ECC , such as Single Event Upset (SEU) mitigation,Single Event Functional Interrupt (SEFI) protection (described in paragraph 4.2) and weak bit mitigation to be able to work in radiation environments.

In addition to the memory controller IP within the RIMC IP core, the user can either select PHY IPs provided in the IP core or develop its own PHY IP.

The RIMC has two primary interfaces, the user interface (UIF) and the DDR memory interface (DIF).

The UIF is comprised of at least one AHB bus, AXI bus or UPI, and also contains an APB bus for user dynamic configuration:

• Slave APB interface dedicated to internal registers
• Optional slave AHB/AXI interface
• Optional UPI interface (compatible with Xilinx MIG)
• Optional Bypass interface