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6 Gbit DDR2 SDRAM (3D2D6G48UB3687)

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The 8-bit interface and is selected with specific #CS, CKE, #CK and CK.

Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality.

It is particularly well suited for use in high reliability, high per­formance and high density system applications, such as solid state mass recorder, server or workstation.
The 3D2D1G08US1285 is packaged in a 74 pin SOP.

Fabio Asti

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Fabio Asti
Business Developement Manager
+39 342 198 3878 fabio.asti@steliau.it
  • Organized as 128M × 48.
  • Supply voltage: 1.8 V ± 0.1 V.
  • JEDEC standard 1.8 V I/O (SSTL_18 compatible).
  • Maximum data rate: 333 MHz.
  • Differential data strobe per byte.
  • 4n-bit prefetch architecture.
  • DLL to align DQ and DQS transitions with CK.
  • 6 internal banks per die for concurrent operation.
  • Programmable CAS Latency.
  • Posted CAS Additive Latency.
  • Write Latency = Read Latency − 1 tCK.
  • Programmable Burst Lengths:

    • 4
    • 8
  • On-Die Termination (ODT).
  • Available temperature range:

    • 0°C to +70°C
    • -40°C to +85°C
    • Specific temperature range available upon request.
  • Available with screening option for high reliability applications (Space, etc.).
  • 3D PLUS DDR2 Radiation Hardened Solution:

    • TID > 100 Krad (Si).
    • SEL immune > 68 MeV·cm²/mg.
    • SEU immune by design (3.8E-9 upsets/SEU/day/module with 3DIPMC700).
    • SEFI immune by design (with 3DIPMC700).

Description

The 3D2D6G48UB3687 is a high-speed highly integrat­ed DDR2 Synchronous Dynamic Ram Memory.

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